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| Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Features s General Description The quad programmable line card signal processor consists of four independent channels of codec and digital signal processing functions on one chip. In addition to the classic A-to-D and D-to-A conversion, the device includes termination impedance synthesis and a 64-tap echo canceller, functionally, on a perchannel basis. The device is capable of meeting all international standards for terminating impedance and digital encoding format. The processing circuitry for the adjustment of the transmit level (equalization) to accommodate current-sensing SLICs is also included. The device is controlled by a serial microprocessor interface, and a set of bidirectional I/O pins are provided, on a per-channel basis, so that this control mechanism can be utilized to operate the battery feed device, ringing voltage switches, etc. Common data and clock paths can be shared over any number of devices. All the filter coefficients, signal processing, SLIC, and test features are accessible through this interface. This serial interface can be operated at speeds up to 4.096 Mbits/s. The PCM bus is also programmable, with any channel capable of being assigned to any time slot. The PCM bus can be operated at speeds up to 16.384 Mbits/s, allowing for a maximum of 256 time slots. Separate transmit and receive interfaces are available for 4-wire bus designs, or they can be strapped together for a 2-wire PCM bus. The device is available in 68-pin, 64-pin, and 44-pin surface-mount packages for economic use of board space. Includes codec, termination impedance, and echo canceller in one device for line card applications Programmable -law, linear, or A-law PCM input and output (ITU-T G.712 compliant) Per-channel programmable gains Per-channel programmable internal termination impedance Per-channel 64-tap echo canceller (ITU-T G.168 compliant) Fully programmable time-slot assignment Analog and digital loopback test modes Serial microprocessor interface Sigma-delta converters with dither to reduce noise Six per-channel, bidirectional control pins for SLIC and line card function control (68-pin package) Quad design to minimize package count on dense line card applications Built-in level correction (transmit equalization) to accommodate current-sensing SLICs Single 5 V operation Available in 68-pin, 64-pin, and 44-pin packages s s s s s s s s s s s s s T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Table of Contents Contents Page Figure 9. Write Operation, Byte-by-Byte Mode (Continuous DCLK) .................................. 15 Figure 10. Write Operation, Byte-by-Byte Mode (Gapped DCLK) ...................................... 15 Figure 11. Read Operation, Normal Mode (Continuous DCLK) ................................ 16 Figure 12. Read Operation, Normal Mode (Gapped Clock) ...................................... 17 Figure 13. Read Operation, Byte-by-Byte Mode (Continuous DCLK) ................................ 18 Figure 14. Read Operation, Byte-by-Byte Mode (Gapped DCLK) ...................................... 19 Figure 15. Fast Scan, Normal Mode (Continuous DCLK) ................................ 20 Figure 16. Fast Scan, Normal Mode (Gapped DCLK) ...................................... 21 Figure 17. Fast Scan, Byte-by-Byte Mode (Continuous DCLK) ................................ 22 Figure 18. Fast Scan, Byte-by-Byte Mode (Gapped DCLK) ...................................... 22 Figure 19. Hardware Reset Procedure .................... 23 Figure 20. Internal Signal Processing ...................... 26 Figure 21. Serial Interface Timing, Normal Mode (One Byte Transfer Shown) .................... 36 Figure 22. Serial Interface Timing, Byte-by-Byte Mode (One Byte Transfer and Gapped DCLK Shown) ......................................... 36 Figure 23. PCM Bus Timing (Diagram Shown has Bit Offset of Zero and Minimum Width of FS) .......................................................... 37 Figure 24. POTS Interface ....................................... 44 Features ......................................................................1 General Description.....................................................1 Functional Description .................................................3 Pin Information ............................................................5 Functional Description ...............................................11 Clocking Considerations .........................................11 The Control Interface ..............................................11 Modes ..................................................................11 Protocol ................................................................12 Write Command ...................................................14 Read Command ...................................................16 Fast Scan Mode ...................................................20 Write All Channels................................................23 Reset Functionality .................................................23 Memory Control Mapping .....................................24 Standby Mode.........................................................24 Test Capabilities .....................................................24 Echo Canceller Functionality ..................................25 SLIC Control Capabilities ........................................25 Suggested Initialization Procedures........................25 Signal Processing ...................................................26 Absolute Maximum Ratings.......................................26 Operating Ranges ....................................................27 Handling Precautions ................................................27 Electrical Characteristics ...........................................27 dc Characteristics ...................................................27 Analog Interface......................................................28 Transmission Characteristics ..................................29 Noise Characteristics ..............................................31 Distortion and Group Delay.....................................32 Crosstalk .................................................................33 Timing Characteristics ...............................................34 Bus Timing Diagrams ................................................36 Normal Mode ..........................................................36 Byte-by-Byte Mode .................................................36 PCM Interface .........................................................37 Applications ...............................................................44 Outline Diagrams.......................................................45 68-Pin PLCC ...........................................................45 64-Pin TQFP ...........................................................46 44-Pin PLCC ...........................................................47 Ordering Information..................................................48 Tables Page Figures Page Figure 1. Functional Block Diagram, Each Section ....3 Figure 2. 44-Pin PLCC Pin Diagram........................... 5 Figure 3. 68-Pin PLCC Pin Diagram ...........................7 Figure 4. 64-Pin TQFP Pin Diagram ...........................9 Figure 5. Command Frame Format, Master to Slave, Read or Write Commands .........................13 Figure 6. Command Frame Format, Slave to Master, Read Commands ......................................13 Figure 7. Write Operation, Normal Mode (Continuous DCLK) ...................................14 Figure 8. Write Operation, Normal Mode (Gapped DCLK) .........................................14 2 Table 1. Pin Assignments, 44-Pin PLCC, Per-Channel Functions ................................ 5 Table 2. Pin Assignments, 44-Pin PLCC, Common Functions .................................... 6 Table 3. Pin Assignments, 68-Pin PLCC, Per-Channel Functions ................................ 7 Table 4. Pin Assignments, 68-Pin PLCC, Common Functions .................................... 8 Table 5. Pin Assignments, 64-Pin TQFP, Per-Channel Functions ................................ 9 Table 6. Pin Assignments, 64-Pin TQFP, Common Functions .................................. 10 Table 7. Bit Assignments for Fast Scan Mode ....... 20 Table 8. dc Characteristics ..................................... 27 Table 9. Analog Interface ....................................... 28 Table 10. Power Requirements .............................. 29 Table 11. Transmission Characteristics ................. 29 Table 12. Per-Channel Noise Characteristics ........ 31 Table 13. Distortion and Group Delay ..................... 32 Table 14. Crosstalk .................................................. 33 Table 15. Timing Characteristics ............................. 34 Table 16. Echo Canceller Characteristics ............... 35 Table 17. Memory Mapping ..................................... 38 Table 18. Control Bit Definition ................................ 39 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Functional Description Refer to Figure 1 for the following discussion. (It should be noted that much of the processing is performed in a digital processor; thus, the actual data flow may be different than this functional, analog analogy based diagram shows.) ANALOG GAIN VFXINn A/D CONVERTER DIGITAL LOOPBACK 3 DIGITAL LOOPBACK 2 ANALOG LOOPBACK DIGITAL GAIN (GAIN TRANSFER) PER CHANNEL 18 COMMON POWER AND GROUND - DIGITAL LOOPBACK 4 -LAW OR A-LAW CONVERSION DIGITAL LOOPBACK 1 DX TO/FROM SLIC TERMINATION IMPEDANCE ECHO CancellER PCM BUS INTERFACE TO/FROM PCM BUS VFROPn D/A CONVERTER VFRONn ANALOG BUFFER DIGITAL GAIN (GAIN TRANSFER) CONTROL AND DATA SIGNALS FS BCLK DR SLIC CONTROL LATCHES 0 TO 6 PER CHANNEL MICROPROCESSOR CONTROL FREQUENCY SYNTHESIZER 3 FACTORY TEST COMMON 4 RST SERIAL CONTROL INTERFACE 5-7172.ar5(F) MCLK Figure 1. Functional Block Diagram, Each Section This device performs virtually all the signal processing functions associated with a central office line termination. Functionality includes line termination impedance synthesis, adaptive or fixed hybrid balance (echo canceller), and level conversion both in the analog sense (transmit equalization), to accommodate various subscriber line interface circuits (SLICs), and in the digital sense, for adjustment of the levels on the PCM bus (gain transfer). In general, the termination impedance synthesis generates the equivalent of a circuit with the parallel combination of a capacitor and a resistor in series with a resistor or the parallel combination of a resistor and the series combination of a resistor and capacitor. These general forms of impedance characteristic will satisfy most of the requirements specified throughout the world. Programmable selection of either -law or A-law encoding further aids worldwide deployment. In addition to the programmable features for impedance and coding, the device also contains an echo canceller that meets international requirements for network echo cancellers. This includes the ability to automatically disable the adaptation in the presence of 2100 Hz modem tones. All coefficients used in the filtering algorithms can be computed off-line in advance and downloaded to the device at the time of powerup. All signal processing is contained within the device, and there are only three interfaces of consequence to the system designer: the SLIC interface, the PCM interface, and the control interface. Agere Systems Inc. 3 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 The microprocessor control interface is a serial interface that uses the classic chip select type of operation. The interface controls the device by writing or reading various internal addresses. The command set comprises simple read and write operations, with the address determining the effect. All the memory locations, including the per-chip functions, are organized by channel, allowing a straightforward migration path to architectures other than quad. There are several test modes included to facilitate confirmation of correct operation. In the signal path, both an analog and four digital loopback tests are available, while in the microprocessor interface, there is a write/read test mode that tests the operation of the memory. Use of external test access switches allows a complete test of the signal path through the line card so that correct operation of various operational modes can be verified. Functional Description (continued) The SLIC interface is designed to be flexible and convenient to use with a variety of SLIC circuits. With an appropriate choice of SLIC, no external components are required in the interface, with the exception of a dc blocking capacitor in the transmit direction. In some cases, dc blocking capacitors in the receive direction may be necessary as well, since the device operates from a single 5 V supply. The PCM bus interface is flexible in that it allows, independently, the transmit and receive data for any channel to be placed in any time slot. The bus can be operated at a maximum of a 16.384 Mbits/s rate to accommodate a maximum of 256 time slots. Separate pins are provided for each direction of transmission to allow 4-wire bus operation. The frame strobe signal is an 8 kHz signal that defines the beginning of the frame structure. The interface will count 8 bits per time slot and insert or read the data for each channel as programmed. Lower speeds of the PCM bus are allowed. The PCM clock must be synchronous with the master clock for the device (if present) and with the frame strobe signal. 4 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Pin Information DGND MCLK FILTV DCLK INTS RST VDD DO 6 PVCOIN PVCO PLLT SGND VFRONa VFROPa VFXIa VDDa AGNDa DGND VDD 7 8 9 10 11 12 13 14 15 16 17 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 DX DGND BCLK FS VDD VFRONd VFROPd VFXId VDDd AGNDd DGND DR 34 33 32 31 30 29 28 VDD CS DI 22 AGNDb T8533 18 19 VFRONb VFROPb 20 VFXIb 21 VDDb 23 AGNDc 24 VDDc 25 VFXIc 26 VFROPc 27 VFRONc 5-8195(F) Figure 2. 44-Pin PLCC Pin Diagram Table 1. Pin Assignments, 44-Pin PLCC, Per-Channel Functions Ckt a b c d 15 22 23 30 14 21 24 13 20 25 12 19 26 11 18 27 Name AGND Type Name/Description GND Analog Ground. A common AGND, DGND, SGND plane is highly recommended. PWR 5 V Analog Power Supply. 31 VDD I Transmit Analog Input. For complex terminations, this node requires a 10 M 32 VFXI or 20 M resistance to AGND. O Receive Analog Output, Positive Polarity. 33 VFROP O Receive Analog Output, Negative Polarity. 34 VFRON Agere Systems Inc. 5 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Pin Information (continued) Table 2. Pin Assignments, 44-Pin PLCC, Common Functions Pin 1 2 3 4 5 Name DO DI DCLK CS INTS Type O I I I I Name/Description Serial Data Output. This is a 3-state output. Serial Data Input. Serial Data Clock Input. Chip Select Input. This pin determines the interval that the serial interface is active. Serial Interface Select. Leaving this pin open places the serial interface in the normal mode; grounding it places the interface into the byte-by-byte mode. This pin has an internal pull-up. Frequency Synthesizer Power (5 V). This pin must be tied to VDD. Internal Test Point. Do not connect to this pin. Internal Test Point. Do not connect to this pin. Internal Test Point. Do not connect to this pin. Synthesizer Ground. Connect to DGND. A common AGND, DGND, SGND plane is highly recommended. Digital Ground. Logic ground and return for logic power supply. A common AGND, DGND, SGND plane is highly recommended. Digital Power Supply (5 V). PCM Frame Strobe Input. This 8 kHz clock must be derived from the same source as BCLK. See the Clocking Considerations section. PCM Clock Input. This pin is used to develop internal clocks for certain clock rates. See the Clocking Considerations section. PCM Bus Output Pin. This is a 3-state output. PCM Bus Input Pin. Power-On Reset. A low causes a reset of the entire chip. This pin may be connected to DGND with a 0.1 F capacitor for a power-on reset function, or it may be driven by external logic. This pin has an internal pull-up. 1.024 MHz Master Clock Input. Internal timing is derived from this clock input for certain PCM bus rates. See Clocking Considerations. When unused, this pin may be left open. This pin has an internal pull-up. 6 7 8 9 10 16, 29, 38, 44 17, 28, 35, 42 36 37 39 40 41 FILTV PVCOIN PVCO PLLT SGND DGND VDD FS BCLK DX DR RST PWR -- -- -- GND GND PWR I I O I I 43 MCLK I 6 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Pin Information (continued) SLIC2a SLIC3a SLIC4a SLIC5a INTS CS DCLK DI DO DGND MCLK VDD RST SLIC4d SLIC3d SLIC5d SLIC2d 9 8 7 6 5 4 3 2 1 68 67 66 6564 63 6261 FILTV PVCOIN PVCO PLLT SGND SLIC1a SLIC0a VFRONa VFROPa VFXIa VDDa AGNDa SLIC5b SLIC4b DGND SLIC3b SLIC2b 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 DR DX DGND BCLK FS VDD SLIC1d SLIC0d VFRONd VFROPd VFXId VDDd AGNDd SLIC5c SLIC4c DGND SLIC3c T8534 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 SLIC1b VDD SLIC0b VFRONb VFROPb VFXIb VDDb AGNDb AGNDc VDDc VFXIc VFROPc VFRONc VDD SLIC0c SLIC1c SLIC2c 5-8194(F) Figure 3. 68-Pin PLCC Pin Diagram Table 3. Pin Assignments, 68-Pin PLCC, Per-Channel Functions Ckt a b c d 21 34 35 48 Name AGND Type Name/Description GND Analog Ground. A common AGND, DGND, SGND plane is highly recommended. PWR 5 V Analog Power Supply. 20 33 36 49 VDD I Transmit Analog Input. For complex terminations, this node requires a 10 M 19 32 37 50 VFXI or 20 M resistance to AGND. O Receive Analog Output, Positive Polarity. 18 31 38 51 VFROP O Receive Analog Output, Negative Polarity. 17 30 39 52 VFRON 16 29 41 53 SLIC0 I/O SLIC Control Pin 0. 15 27 42 54 SLIC1 I/O SLIC Control Pin 1. 9 26 43 61 SLIC2 I/O SLIC Control Pin 2. 8 25 44 63 SLIC3 I/O SLIC Control Pin 3. 7 23 46 64 SLIC4 I/O SLIC Control Pin 4. 6 22 47 62 SLIC5 I/O SLIC Control Pin 5. Agere Systems Inc. 7 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Pin Information (continued) Table 4. Pin Assignments, 68-Pin PLCC, Common Functions Pin 1 2 3 4 5 Name DO DI DCLK CS INTS Type O I I I I Name/Description Serial Data Output. This is a 3-state output. Serial Data Input. Serial Data Clock Input. Chip Select Input. This pin determines the interval that the serial interface is active. Serial Interface Select. Leaving this pin open places the serial interface in the normal mode; grounding it places the interface into the byte-by-byte mode. This pin has an internal pull-up. Frequency Synthesizer Power (5 V). This pin must be tied to VDD. Internal Test Point. Do not connect to this pin. Internal Test Point. Do not connect to this pin. Internal Test Point. Do not connect to this pin. Synthesizer Ground. Connect to DGND. A common AGND, DGND, SGND plane is highly recommended. Digital Ground. Logic ground and return for logic power supply. A common AGND, DGND, SGND plane is highly recommended. Digital Power Supply (5 V). PCM Frame Strobe Input. This 8 kHz clock must be derived from the same source as BCLK. See the Clocking Considerations section. PCM Clock Input. This pin is used to develop internal clocks for certain clock rates. See the Clocking Considerations section. PCM Bus Output Pin. This is a 3-state output. PCM Bus Input Pin. Power-On Reset. A low causes a reset of the entire chip. This pin may be connected to DGND with a 0.1 F capacitor for a power-on reset function, or it may be driven by external logic. This pin has an internal pull-up. 1.024 MHz Master Clock Input. Internal timing is derived from this clock input for certain PCM bus rates. See the Clocking Considerations section. When unused, this pin may be left open. This pin has an internal pull-up. 10 11 12 13 14 24, 45, 58, 68 28, 40, 55, 66 56 57 59 60 65 FILTV PVCOIN PVCO PLLT SGND DGND VDD FS BCLK DX DR RST PWR -- -- -- GND GND PWR I I O I I 67 MCLK I 8 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Pin Information (continued) SLIC2a SLIC3a SLIC4a INTS CS DCLK DI DO DGND MCLK VDD RST SLIC4d SLIC3d SLIC2d DR 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 FILTV PVCOIN PVCO PLLT SGND SLIC1a SLIC0a VFRONa VFROPa VFXIa VDDa AGNDa SLIC4b DGND SLIC3b SLIC2b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DX DGND BCLK FS VDD SLIC1d SLIC0d VFRONd VFROPd VFXId VDDd AGNDd SLIC4c DGND SLIC3c SLIC2c T8534 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SLIC1b VDD SLIC0b VFRONb VFROPb VFXIb VDDb AGNDb AGNDc VDDc VFXIc VFROPc VFRONc VDD SLIC0c SLIC1c 5-8196(F) Figure 4. 64-Pin TQFP Pin Diagram Table 5. Pin Assignments, 64-Pin TQFP, Per-Channel Functions Ckt a b c d 12 24 25 37 Name AGND Type Name/Description GND Analog Ground. A common AGND, DGND, SGND plane is highly recommended. PWR 5 V Analog Power Supply. 11 23 26 38 VDD I Transmit Analog Input. For complex terminations, this node requires a 10 M 10 22 27 39 VFXI or 20 M resistance to AGND. O Receive Analog Output, Positive Polarity. 9 21 28 40 VFROP O Receive Analog Output, Negative Polarity. 8 20 29 41 VFRON 7 19 31 42 SLIC0 I/O SLIC Control Pin 0. 6 17 32 43 SLIC1 I/O SLIC Control Pin 1. 64 16 33 50 SLIC2 I/O SLIC Control Pin 2. 63 15 34 51 SLIC3 I/O SLIC Control Pin 3. 62 13 36 52 SLIC4 I/O SLIC Control Pin 4. Agere Systems Inc. 9 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Pin Information (continued) Table 6. Pin Assignments, 64-Pin TQFP, Common Functions Pin 1 2 3 4 5 14, 35, 47, 56 18, 30, 44, 54 45 46 48 49 53 Name FILTV PVCOIN PVCO PLLT SGND DGND VDD FS BCLK DX DR RST Type PWR -- -- -- GND Name/Description Frequency Synthesizer Power (5 V). This pin must be tied to VDD. Internal Test Point. Do not connect to this pin. Internal Test Point. Do not connect to this pin. Internal Test Point. Do not connect to this pin. Synthesizer Ground. Connect to DGND. A common AGND, DGND, SGND plane is highly recommended. GND Digital Ground. Logic ground and return for logic power supply. A common AGND, DGND, SGND plane is highly recommended. PWR Digital Power Supply (5 V). I PCM Frame Strobe Input. This 8 kHz clock must be derived from the same source as BCLK. See the Clocking Considerations section. I PCM Clock Input. This pin is used to develop internal clocks for certain clock rates. See the Clocking Considerations section. O PCM Bus Output Pin. This is a 3-state output. I PCM Bus Input Pin. I Power-On Reset. A low causes a reset of the entire chip. This pin may be connected to DGND with a 0.1 F capacitor for a power-on reset function, or it may be driven by external logic. This pin has an internal pull-up. I 1.024 MHz Master Clock Input. Internal timing is derived from this clock input for certain PCM bus rates. See the Clocking Considerations section. When unused, this pin may be left open. This pin has an internal pull-up. O Serial Data Output. This is a 3-state output. I Serial Data Input. I Serial Data Clock Input. I Chip Select Input. This pin determines the interval that the serial interface is active. I Serial Interface Select. Leaving this pin open places the serial interface in the normal mode; grounding it places the interface into the byte-by-byte mode. This pin has an internal pull-up. 55 MCLK 57 58 59 60 61 DO DI DCLK CS INTS 10 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor All data transfers on the serial bus are byte oriented with the least significant bit (shown in this data sheet as bit 0) transmitted first, followed by the more significant bits. For data fields, the least significant byte of the first data byte is transmitted first, followed by the more significant bytes, each byte transmitted LSB first. This format is compatible with the serial port on most microcontrollers. Modes There are two different modes of operation for the serial interface, the normal mode and the byte-by-byte mode. These two modes differ in the manner in which CS is used to control the transfer. Note that the CS lead is used to control the transfer of serial data from master controller to slave codec and in the reverse direction. In normal mode, (INTS pin open) the CS lead must go low for the duration of the transfer. The only error check performed by the codec is to verify that CS is low for an integral number of bytes. Detection of an active (activelow) chip select for other than an integral multiple of 8 bits results in the operation being terminated. The next active excursion of chip select will be interpreted as a new command; hence, the serial I/O interface can always be initialized by asserting CS for a number of clock periods that is not an integral multiple of 8. CS is captured using DCLK, so DCLK must be transitioned to perform this initialization. Undefined command codes are reserved for future use and may cause unwanted operation of the device. The byte-by-byte mode (INTS pin tied to ground) uses CS to control each byte of the transfer. In this mode, CS goes low for exactly 8 bits at a time, corresponding to a 1-byte transfer either to or from the codec chip. Repeated transitions of CS are used to control subsequent bytes of data to/from the codec. For a write command in this mode, CS must go low for each byte of the transfer until the transfer is complete. For a read command, CS will go low for each of the 3 bytes of the read command transferred to the device, then low again for each byte to be read. Notice that the total number of bytes transferred (and excursions on CS) is N + 3, where N is the number of bytes to be read in the command. This mode of operation is useful in cases where the master is a microprocessor with a built-in UART that transfers 1 byte at a time. Error detection is limited to detection of an active CS for other than an integral multiple of 8 bits. Recovery is the same as normal mode. Note that the clock phase is shifted in this mode. Flow control can be accomplished by suspending the transitions on DCLK by holding either state. During the data transfer, CS must remain low while clock transitions are suspended with DCLK in either state. 11 Functional Description Clocking Considerations This device has several clock inputs for the various interfaces. The PCM bus uses BCLK as the bit clock and the one-going edge of FS to determine the location of the beginning of a frame. These two clocks must be derived from the same source. Internally, the device develops all the internal clocks with a phase-locked loop that uses BCLK as the timing source when BCLK is 16.384, 8.192, 4.096, 2.048, or 1.024 MHz. In these instances, MCLK is not used and may be left open since any signal driving MCLK is ignored. For BCLK rates of 256 kHz and 512 kHz, MCLK is used as a source for the PLL and must be 1.024 MHz. In this latter case, BCLK, MCLK, and FS must be derived from the same source and the rising edge of BCLK must be within 10 ns of the rising edge of MCLK. BCLK, FS, and MCLK (if required) must be continuously present and without gaps in order for the device to operate correctly. Note that the nominal values in Table 15 are the valid frequencies for BCLK. DCLK is used to clock the internal serial interface and may be asynchronous to the other clocks. There is no need to derive this clock from the same source as the other clocks. The serial bus may be operated at any speed up to 4.096 Mbits/s. DCLK can be gapped, however additional clock cycles are required in and around the command frame to process data, and during and after a hardware or a software reset to ensure complete clearing of internal logic. There is no limit on the number of devices on the same serial bus. The Control Interface The device is controlled via a series of memory locations accessed by a serial data connection to the external master controller. This interface operates using the chip select lead to enable transmission of information. All chip functions are enabled or disabled by setting or clearing bits in the control memory. Filter coefficients and gain adjustments are also stored in this memory. The codec has both a serial input lead and a serial output lead. These may be used individually for a 4-wire serial interface, or tied together for a 2-wire interface. The line driver circuitry is capable of driving relatively high currents so that in the event that the line is long enough to show significant transmission line effects, it can be terminated in the characteristic impedance at each end with resistors to VCC and ground. Agere Systems Inc. T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 There is no response from the slave to the master for a write operation. The response to a read operation simply includes the data to be read in the data field. This data is sent least significant bit first, with the bytes sent in ascending sequence. Commands from the master controller include data for write operations, but not for read operations. Since the coefficients and gains are stored in volatile memory, all the coefficients and gains must be loaded after powerup. There is, however, no need to reload them when switching from active to standby modes, or vice versa. Great care should be exercised in loading memory when the codec channel is not in standby mode. Sudden changes in the termination or balance impedances can result in undesirable system operation. All data is transmitted in a byte-oriented fashion with the least significant bit of each byte transferred first. Multibyte fields are transferred least significant byte first in both directions. The data field will contain the first addressed data location first, with subsequent data locations transmitted in ascending order. Functional Description (continued) The Control Interface (continued) Protocol The format of the command protocol is shown in Figures 5 and 6. The control interface operates with one external master controller and multiple slave codec devices. Each transfer is initiated by the master, and the slave responds for either read operations or the fast scan mode. The slave does not check the bus for activity prior to transmitting; it only checks for an active CS. The master should allow for a wait between the end of a read command until CS becomes active for the read data. The master must refrain from sending additional commands to the slave chip until the response is received. On a 4-wire bus, commands to other devices may be initiated before the response is received, but care in generating the CS function is needed to ensure that the multiple responses do not interfere. It should be noted that multiple memory locations can be accessed in the same command by setting the data field length field to the desired number of bytes to be transferred. If flow control is desired, it must be performed by using separate commands, each transferring smaller blocks of information, or by controlling the serial clock (gapping the serial clock), or with CS in the case of byte-by-byte mode. 12 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Functional Description (continued) The Control Interface (continued) Protocol (continued) LSB MSB LSB TIME MSB LSB MSB LSB DATA FIELD (VARIABLE LENGTH) WRITE OPERATIONS ONLY COMMAND (8 bits) START ADDRESS (8 bits) DATA FIELD LENGTH (8 bits) 7 MSB START ADDRESS: 7 MSB DATA FIELD LENGTH: 7 MSB COMMAND: 0* 6 5 4 3 2 1 0 LSB 6 5 4 3 2 1 0 LSB 6 0* 5 4 3 0 2 0 1 0 LSB CKT SELECT COMMAND CKT SELECT: CKT a: CKT b: CKT c: CKT d: 00 01 10 11 COMMANDS: FAST SCAN MODE: WRITE MEMORY: WRITE ALL CHANNELS: READ MEMORY: 10 01 11 00 * Location of memory bank selection. All user controls are in memory bank 0; other memory banks contain internal state information for the device. Note: Data field length is in bytes for all operations. All data is transmitted in bytes with the LSB for each byte transmitted first. For 16-bit memory operations, the least significant byte of the first memory location is transmitted first, followed by the most significant byte; each byte is transmitted LSB first. Additional memory locations are loaded in ascending sequence. Figure 5. Command Frame Format, Master to Slave, Read or Write Commands LSB DATA FIELD (VARIABLE LENGTH) READ OPERATIONS ONLY Note: All data is transmitted in bytes with the LSB for each byte transmitted first. For memory operations, the least significant byte of the first memory location is transmitted first, followed by the most significant byte, each byte transmitted LSB first. Additional memory locations are loaded in ascending sequence. Figure 6. Command Frame Format, Slave to Master, Read Commands Agere Systems Inc. 13 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Functional Description (continued) The Control Interface (continued) Write Command A write command is used to write to the memory addresses. Figures 7--10 illustrate normal or byte-by-byte operation with continuous or gapped DCLKs. For gapped DCLK operation, transitions, not frequency, are critical (as long as transitions occur no faster than 122 ns apart). COMMAND FRAME CS COMMAND START ADDRESS LENGTH DATA * DCLK 0 1 7 0 1 7 0 1 7 0 1 7 DI 0 1 7 0 1 7 0 1 7 0 1 7 0078 * Two or more full DCLK cycles are required before the start of a new command frame. Note: Data field length of 1 shown. Figure 7. Write Operation, Normal Mode (Continuous DCLK) COMMAND FRAME CS COMMAND START ADDRESS LENGTH DATA CK1 CK2 CK3 7 DCLK 0 1 7 0 1 7 0 1 7 0 1 7 DI 0 1 7 0 1 7 0 1 7 0 1 CK4 0076 Notes: Data field length of 1 shown. CK1 through CK4 are additional DCLK pulses required to properly process the data. CK3 and CK4 are not necessary if another command frame follows this sequence. Figure 8. Write Operation, Normal Mode (Gapped DCLK) 14 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Functional Description (continued) The Control Interface (continued) Write Command (continued) COMMAND FRAME CS COMMAND START ADDRESS LENGTH DATA ONE OR MORE FULL DCLK CYCLES REQUIRED HERE DCLK 0 1 7 0 1 7 0 1 7 0 1 7 * DI 0 1 7 0 1 7 0 1 7 0 1 7 0074 * Two or more full DCLK cycles are required before the start of a new command frame. Note: Data field length of 1 shown. Figure 9. Write Operation, Byte-by-Byte Mode (Continuous DCLK) COMMAND FRAME COMMAND START ADDRESS LENGTH DATA CS CK1 CK2 CK3 DCLK 0 1 7 0 1 7 0 1 7 0 1 7 DI 0 1 7 0 1 7 0 1 7 0 1 7 0072 Notes: Data field length of 1 shown. CK1 through CK4 are additional DCLK pulses required to properly process the data. CK3 and CK4 are not necessary if another command frame follows this sequence. Figure 10. Write Operation, Byte-by-Byte Mode (Gapped DCLK) Agere Systems Inc. CK4 15 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Functional Description (continued) The Control Interface (continued) Read Command The normal flow of information to the master controller is always in response to a read command. All control memory locations are accessed in 8-bit bytes. All read commands from the master controller require a response from the addressed codec. It is the responsibility of the master controller to ensure that only one device is transmitting on the serial interface line at any one time. The master controller also must ensure that the CS lead goes high after transferring the 3-byte sequence used to initiate the read, and then it goes low again for the response. In this case, it should be noted that the device expects the second time CS goes low that data is to be sent to the master; thus, it does not interpret the DI lead as containing a valid instruction during that CS excursion and a write during this time is not recommended. Note also that the CS lead must allow the number of bytes sent in a read command to be transferred before a subsequent command can be received by the codec. Figures 11--14 illustrate normal or byte-by-byte operation with continuous or gapped DCLKs. Like a write command, transitions, not frequency, are critical with regard to gapped DCLK operation. COMMAND FRAME CS COMMAND START ADDRESS LENGTH WAIT 1.5 s DATA DCLK 0 1 7 0 1 7 0 1 7 * 0 1 7 DI 0 1 7 0 1 7 0 1 7 DO 0 1 7 0079 * Provide sufficient wait time to access read data. Provide sufficient DCLK cycles to effectively wait 1.5 s after the second full DCLK cycle and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between LENGTH and DATA. The first two DCLK cycles, when CS goes high, processes the command. A wait is then required to access the read data. Two final DCLK cycles are required to process the read data. Two or more DCLK cycles are required before the start of a new command frame. Note: Data field length of 1 shown. Figure 11. Read Operation, Normal Mode (Continuous DCLK) 16 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Functional Description (continued) The Control Interface (continued) Read Command (continued) COMMAND FRAME CS COMMAND START ADDRESS LENGTH WAIT 1.5 s DATA CK1 CK2 CK3 CK4 CK5 CK6 CK7 7 DCLK 0 1 7 0 1 7 0 1 7 0 1 7 DI 0 1 7 0 1 7 0 1 7 DO 0 1 CK8 0077 Notes: Data field length of 1 shown. CK1 through CK8 are additional DCLK pulses required to properly process the data. CK7 and CK8 are not necessary if another command frame follows this sequence. Figure 12. Read Operation, Normal Mode (Gapped Clock) Agere Systems Inc. 17 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Functional Description (continued) The Control Interface (continued) Read Command (continued) COMMAND FRAME START ADDRESS CS COMMAND LENGTH DATA ONE OR MORE FULL DCLK CYCLES REQUIRED HERE WAIT 1.5 s DCLK 0 1 7 0 1 7 0 1 7 * 0 1 7 DI 0 1 7 0 1 7 0 1 7 D0 0 1 7 0075 * Provide sufficient wait time to access read data. Provide sufficient DCLK cycles to effectively wait 1.5 s after the second full DCLK cycle and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between LENGTH and DATA. The first two DCLK cycles, when CS goes high, processes the command. A wait is then required to access the read data. Two final DCLK cycles are required to process the read data. Two or more DCLK cycles are required before the start of a new command frame. Note: Data field length of 1 shown. Figure 13. Read Operation, Byte-by-Byte Mode (Continuous DCLK) 18 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Functional Description (continued) The Control Interface (continued) Read Command (continued) COMMAND FRAME START ADDRESS CS COMMAND LENGTH WAIT 1.5 s DATA CK1 CK2 CK4 CK6 DCLK 0 1 7 0 1 7 0 1 7 0 1 7 DI 0 1 7 0 1 7 0 1 7 D0 0 1 7 0073 Notes: Data field length of 1 shown. CK1 through CK8 are additional DCLK pulses required to properly process the data. CK7 and CK8 are not necessary if another command frame follows this sequence. Figure 14. Read Operation, Byte-by-Byte Mode (Gapped DCLK) Agere Systems Inc. CK8 CK3 CK5 CK7 19 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Functional Description (continued) The Control Interface (continued) Fast Scan Mode The fast scan mode allows a single byte command to read two SLIC control leads for all four channels with a 1-byte reply. This mode significantly speeds up the normal scanning for off-hook, ring trip, and ring ground detection. This special command sequence allows the controlling microprocessor to fast scan 2 bits in the SLIC control byte of each of the four channels. The command code is (00000010)2, there are no start address or length fields. The command returns only a single byte of data, formatted as shown in Table 9. Table 7. Bit Assignments for Fast Scan Mode Bit 0 (LSB) 1 2 3 4 5 6 7 (MSB) Reported Status Channel 0, bit 0 (ckt a, address 160, bit 0) Channel 0, bit 1 (ckt a, address 160, bit 1) Channel 1, bit 0 (ckt b, address 160, bit 0) Channel 1, bit 1 (ckt b, address 160, bit 1) Channel 2, bit 0 (ckt c, address 160, bit 0) Channel 2, bit 1 (ckt c, address 160, bit 1) Channel 3, bit 0 (ckt d, address 160, bit 0) Channel 3, bit 1 (ckt d, address 160, bit 1) The circuit select in the command structure (Figure 5) is not used for this special single-byte command. The rules for toggling chip select apply as for the read command. Figures 15--18 illustrate normal or byte-by-byte operation with continuous or gapped DCLKs. WAIT 1.5 s CS COMMAND DATA DCLK 0 1 2 3 4 5 6 7 * 0 1 2 3 4 5 6 7 DI DO 0 1 2 3 4 5 6 7 0125 * Provide sufficient wait time to access read data. Provide sufficient DCLK cycles to effectively wait 1.5 s after the second full DCLK cycle and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between COMMAND and DATA. The first two DCLK cycles, when CS goes high, processes the command. A wait is then required to access the read data. Two final DCLK cycles are required to process the read data. Two or more DCLK cycles are required before the start of a new command frame. Figure 15. Fast Scan, Normal Mode (Continuous DCLK) 20 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Functional Description (continued) The Control Interface (continued) Fast Scan Mode (continued) WAIT 1.5 s CS COMMAND DATA CK0 CK1 CK3 CK4 CK5 CK6 CK7 7 DCLK 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 DI DO 0 1 2 3 4 5 6 CK8 0127 Note: CK1 through CK8 are additional DCLK pulses required to properly process the data. Figure 16. Fast Scan, Normal Mode (Gapped DCLK) Agere Systems Inc. 21 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Functional Description (continued) The Control Interface (continued) Fast Scan Mode (continued) WAIT 1.5 s CS COMMAND DATA DCLK 0 1 2 3 4 5 6 7 * 0 1 2 3 4 5 6 7 DI DO 0 1 2 3 4 5 6 7 0124e * Provide sufficient wait time to access read data. Provide sufficient DCLK cycles to effectively wait 1.5 s after the second full DCLK cycle and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between COMMAND and DATA. The first two DCLK cycles, when CS goes high, processes the command. A wait is then required to access the read data. Two final DCLK cycles are required to process the read data. Two or more DCLK cycles are required before the start of a new command frame. Figure 17. Fast Scan, Byte-by-Byte Mode (Continuous DCLK) WAIT 1.5 s CS COMMAND DATA CK0 CK1 CK3 CK4 CK5 CK6 CK7 DCLK 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 DI DO 0 1 2 3 4 5 6 7 0126f Note: CK1 through CK8 are additional DCLK pulses required to properly process the data. Figure 18. Fast Scan, Byte-by-Byte Mode (Gapped DCLK) 22 Agere Systems Inc. CK8 Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Functional Description (continued) The Control Interface (continued) Write All Channels The write all channels command causes all four channels to be loaded with the same coefficients with a single data transfer from the master controller. This allows for a faster initialization of the device after a powerup. This command should be used with caution since it affects all four channels. The normal memory write and read commands affect only one channel. Reset Functionality FS RUNS CONTINUOUSLY BCLK RUNS CONTINUOUSLY RST DCLK (GAPPED) 8 PULSES REQUIRED DURING RESET 12 PULSES REQUIRED AFTER RESET NO GAP IS REQUIRED HERE. WAIT 5 ms DCLK (CONTINUOUS) 8 PULSES REQUIRED DURING RESET 12 PULSES REQUIRED AFTER RESET DEVICE CAN NOW BE PROGRAMMED 0071 Figure 19. Hardware Reset Procedure The reset function allows the internal logic of the device to be set to a known initial condition, either externally by activating the reset lead, or on a per-channel basis through the microprocessor interface by setting and then clearing bits, if required, in address RESCTRL (address 128). These two reset functions have different effects, and each of the software reset functions is a subset of the hardware reset functionality. The primary difference is in the treatment of the internal memory. The hardware reset is assumed to be a result of a catastrophic hardware event, such as a loss of power or an initial powerup. Accordingly, the assumption is made that the internal memory does not contain valid data, and default values for all memory locations are loaded. A software reset, however, can only be initiated if the device is operational (at least the microprocessor interface), so the contents of the memory may indeed be valid; thus, the resets may be more specific. Additionally, software resets only affect the selected channel. Agere Systems Inc. 23 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Test Capabilities The device has several built-in test capabilities that can be used to verify correct operation of the signal processing of the line card. These test functions are accessed in several different control addresses. Five loopback modes are employed (the first four in the list below are digital loopbacks): Digital 1. Allows the digital signal from the PCM bus to be looped back to the PCM bus. This loopback facility can be used to verify correct operation of the PCM bus interface logic, as well as operation of the PCM bus. Allows complete testing of the digital processing capability of the codec by looping the data back at the analog/digital conversion interface. This loopback function is at the digital side of the sigma-delta mode converters and loops analog transmit data back to the analog receive path. This loopback is at the PCM bus interface and loops the transmit data from the line back to the receive path. The analog loopback facility can be used to check the operation of all the signal processing performed in the device, including the conversions to/from analog. Functional Description (continued) Reset Functionality (continued) A 0.1 F capacitor between the RST lead and ground will effectively hold the lead low long enough to reset the device on powerup, allowing for a cost-effective power-on reset function. Notice that the memory must be reloaded through the serial interface after a hardware reset function. For proper operation, it is necessary for FS and BCLK to be present and stable during a reset. DCLK transitions (frequency is not critical as long as the maximum rate is not exceeded) are also required in order for all internal logic to be properly cleared as is a wait period for the internal PLL to stabilize. See the timing diagram shown in Figure 19 for the proper hardware or power-on reset procedure. For a software reset, the control memory should not be accessed for a minimum of 256 s following the reset. Memory Control Mapping Several memory locations are used to control the device. The Software Interface tables (Table 17, Memory Mapping and Table 18, Control Bit Definition) show the memory assignments that are useful in call processing and system testing. It should be noted that other memory locations are used by the device to hold intermediate results and other device state information. Writing to these other locations can cause serious disruptions in the operation of the device and should be avoided. Digital 2. Digital 3. Digital 4. Analog 5. Standby Mode The device enters a low-power standby mode with powerup or software reset, or by programming the CHACTIVE register 129, bit 0. In standby mode, the control interface is active, capable of writing or reading registers. SLIC read and write data latches are also active. Analog signals at VFXI and PCM signals at DR are ignored in this mode. BCLK must be present for proper standby mode operation. Three of these loopback functions (digital 1 and 2, and the analog loopback) can be used with tone generation and reception via the PCM bus. By assigning the transmit and receive time slots identically, a loopback arrangement at the PCM bus can be effectively programmed for signals generated on the line side of the codec. This mode is useful for testing from the line side through the entire device. An optional 16-bit encoding mode is included on a perchannel basis for use in various test scenarios, or for use by an external digital signal processor. This mode of operation differs from the companded modes in both the bit order and the use of multiple time slots on the PCM bus. 24 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor The fast scan mode allows for a minimal data transfer on the serial bus to monitor bits 0 and 1 of the SLIC data memory location (159). If these 2 bits are wired as inputs to the off-hook and/or ring ground detection circuits, a convenient method of rapidly scanning for these two functions is obtained. Bits 2 and 3 default to outputs; thus, they are convenient to provide control of the SLIC state. In any event, all six leads are programmable for maximum flexibility. Functional Description (continued) Echo Canceller Functionality The echo canceller has three sets of coefficient memory storage locations. One, called HPRE, contains the default balance coefficients and can be accessed as memory addresses 0--127. This serves as the coefficients for a fixed balance network (adaptation disabled), or as a starting point for echo cancelllation. The contents of these memory locations do not change with adaptation. The adaptation coefficients, which are added to the corresponding coefficients in HPRE, are stored in the HHAT area. Normally, the user has no need to access these coefficients; thus, these addresses are not described in this data sheet. The HHAT coefficients cover either the first 8, 16, 32, or the entire 64-tap length of the balance filter, depending on the settings in the LMSGAIN address. Note that all echo canceller length options in this control location may not be implemented, but are reserved for future use. A third set of coefficients is contained in HDTA, which are used for special data call functions. Suggested Initialization Procedures It is suggested that upon powerup, a hardware reset be used to set the device into a known state. The serial interface should then be used to load the memory addresses that differ from the default values (the write all channels command is convenient for this function). If other devices are controlled by the SLIC data memory location, then it also should be loaded with a known configuration. After the completion of this sequence, the device is ready to be activated. Depending on the application, the next step may either be normal operation or a set of test sequences. After the initialization of the memory, the device and associated line card devices can be controlled by using memory locations 130, 131, 145, 155, 156, 157, 158, 159, and 129; that is, by supplying the PCM bus time-slot addresses, switching the SLIC into the proper mode, and activating the codec. Within memory location 129, the codec would normally be placed into active mode, with both directions of the PCM bus enabled at the start of a call. At the completion of a call, the codec should be placed into standby mode and the PCM bus disabled. Great caution should be used when changing the memory while the codec is in active mode, since termination impedances, balance impedances, and gains may change. These changes are likely to yield undesirable system effects. It is safe to refresh coefficients that are known to be unchanging in the application. It is always possible to read the memory to verify its contents without deleterious effects on codec operation. Normal operation would load the memory and perform all gain adjustments while the codec is in standby mode. Under no circumstances should memory above address 162 be written, since this section of memory is used for state data and intermediate results. Also, all reserved addresses should not be written. Changing this information may have deleterious effects on system operation. SLIC Control Capabilities Memory locations 158, 159, and 160 are used to control six bidirectional latches that are intended to allow the serial interface to control other line card devices, such as ringing/test switches, telecom electromechanical relays, and SLIC devices. When the TTL latches are configured as outputs, external devices should be set up to sink current from the latch. Location 158 sets the operational mode of these latches as either inputs or outputs. Location 159 specifies what is to be written on the latch leads driven by the device. Location 160 reports the actual state of these leads. It should be noted that a channel control reset forces all of these external leads, except those corresponding to bits 2 and 3, to the high-impedance state, so any inputs connected to bits 0, 1, 4, and 5 should have appropriate pull-up or pull-down resistors (off-chip, if required) to force the external device into a known state at powerup or in the event of a reset. Bits 2 and 3 will reset to outputs with a value of zero. Agere Systems Inc. 25 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Functional Description (continued) Signal Processing Figure 20 details the signal processing functional blocks of one channel of the codec. 0 dB TO 24 dB IN 5 STEPS FROM SLIC GTX1 LPF - A/D SINC3 TEQ GTX2 YLPF * XAG * * LIN.TO COMP TO PCM BUS GAIN TWEAKING GAIN TRANSFER * CTZ * 8 STEPS RTZ ANALOG LPF* GAIN TWEAKING SINC3 * ECHO CANCELLER GAIN TRANSFER XLPF 0 dB TO SLIC SMF RCF 1-bit D/A DIGITAL - D/A * GRX2 * GRX1 COMP TO LIN. FROM PCM BUS 4096 kHz 32 kHz SPEED 8 kHz 0496 F * Programmable blocks. Figure 20. Internal Signal Processing Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational section of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Storage Temperature Range Power Supply Voltage (all pins designated power) Negative Voltage on Any Pin with Respect to Ground Thermal Resistance, Junction to Case (68-pin PLCC) Package Power Dissipation (68-pin PLCC) Thermal Resistance, Junction to Case (64-pin MQFP) Package Power Dissipation (64-pin MQFP) Thermal Resistance, Junction to Case (44-pin PLCC) Package Power Dissipation (44-pin PLCC) Symbol Tstg VDDX VSS RJC PD RJC PD RJC PD Min -55 -- -0.25 -- -- -- -- -- -- Max 150 7 -- 43 930 35 1.14 49 815 Unit C V V C/W mW C/W W C/W mW 26 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Operating Ranges Parameter Ambient Operating Temperature Operating Junction Temperature Symbol TA TJ Min -40 -40 Max 85 125 Unit C C Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Agere Systems Inc. employs a human-body model (HBM) and a charged-device model (CDM) for ESD susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for the CDM. A standard HBM (resistance = 1500 , capacitance = 100 pF) is widely accepted and can be used for comparison. The HBM ESD threshold of >1000 V was obtained by using these circuit parameters: HBM ESD Threshold Voltage Device Voltage T8533/T8534 >2000 Electrical Characteristics For all specifications: TA = -40 C to +85 C, VDD = 5 V 5%, unless otherwise noted. Typical values are for TA = 25 C and VDD = 5 V. Input signal frequency is 1004 Hz, unless otherwise noted. dc Characteristics Table 8. dc Characteristics Parameter Input Voltage Low Input Voltage High Input Current Symbol VIL VIH IIL Test Conditions All inputs All inputs Digital, without pull-up, inputs, GND < VIN < VDD With internal pull-up, VIN = GND (INTS, MCLK, and RST pins) With internal pull-up, VIN = VDD (INTS, MCLK, and RST pins) IL = 3.2 mA IL = -320 A GND < VOUT < VDD IL = -10 mA IL = 10 mA Min -- 2.0 -10 -240 -10 -- 3.5 -30 VDD - 0.5 -- Typ -- -- -- -- -- -- -- -- -- -- Max Unit 0.8 V -- V 10 A 10 10 0.4 -- 30 -- 0.5 A A V V A V V Output Voltage Low Output Voltage High Output Current in High-impedance State Line Driver (DX and DO pins) Output Voltage High Line Driver (DX and DO pins) Output Voltage Low VOL VOH IOZ VOH VOL Agere Systems Inc. 27 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Electrical Characteristics (continued) Analog Interface The following specifications pertain to the analog SLIC interface for each channel. Table 9. Analog Interface Parameter Input Resistance Input Voltage Symbol RVFXI VIX Test Conditions 0.25 < VIN < (VDDX - 0.25) V Relative to ground Signal should be capacitively coupled to VFXI RL RL RL RL Min 100 1.8 Typ -- 2.0 Max Unit 300 k 2.2 V Load Resistance at VFROP and VFRON (differential) RL 7.5 -- -- k 5-8881F Output Resistance Output Offset Voltage Between VFROP and VFRON Output Offset Voltage Between VFROP and VFRON, Standby Mode Common-mode Output Voltage, Active Mode Common-mode Output Voltage, Standby Mode RO VOS VOSS VOCM VOCMS Digital input code corresponding to idle PCM code (-law) Digital input code corresponding to idle PCM code (-law) RL = 100 k Digital input code corresponding to alternating zero -law PCM code -- -- -100 -20 -- 1.7 2 0 0 2.0 2.0 10 100 20 -- 2.3 mV mV V V 28 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Electrical Characteristics (continued) Analog Interface (continued) Table 10. Power Requirements Parameter Operating Voltage: VDD VDDX Power Supply Current, VDD + VDDX: All Channels in Standby Mode All Channels Active Min 4.75 4.75 -- -- Typ -- -- -- -- Max 5.25 5.25 35 110 Unit V V mA mA Transmission Characteristics Table 11. Transmission Characteristics Parameter Absolute Levels Symbol GAL Test Conditions Maximum 0 dBm0 levels (1004 Hz): VFXI (encoder milliwatt), all programmable transmit gains set to 0 dB RCV (decoder milliwatt), termination impedance off, all programmable receive gains set to 0 dB Minimum 0 dBm0 levels (1004 Hz): VFXI (encoder milliwatt) XAG = 24 dB GTX1 = 6 dB GTX2 = 0 dB RCV (decoder milliwatt), termination impedance off GRX1 = 0 dB GRX2 = -6 dB VFXI VFROP to VFRON (differential) Transmit gain programmed for maximum 0 dBm0 test level, measured deviation of digital code from ideal 0 dBm0 level at DX digital outputs, with transmit gain set to 0 dB: 20 C to 70 C 0 C to 85 C -40 C to +85 C Measured transmit gain over the range from maximum to minimum, calculated deviation from the programmed gain relative to GXA at 0 dB, VDD = 5 V Min -- Typ 2.80 Max -- Unit Vp-p -- 5.29 -- Vp-p -- 87.5 -- mVp-p -- 2.63 -- Vp-p Absolute Maximum Voltage Swings Transmit Gain Absolute Accuracy GAL GXA -- -- -- -- 3.2 5.28 Vp-p Vp-p -- -0.25 -0.35 0.15 -- -- -- 0.25 0.35 dB dB dB Transmit Gain Variation GXAG with Programmed Gain -0.1 -- 0.1 dB Agere Systems Inc. 29 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Electrical Characteristics (continued) Transmission Characteristics (continued) Table 11. Transmission Characteristics (continued) Parameter Symbol Test Conditions Transmit Gain Varia- GXAF Relative to 1004 Hz, minimum tion with Fregain < GX < maximum gain, VFXI = 0 dBm0 signal, path gain set to 0 dB: quency, 600 Resistive Source f = 16.67 Hz Impedance and f = 40 Hz Synthesized Termif = 50 Hz nation Impedance f = 60 Hz f = 200 Hz f = 300 Hz to 3000 Hz f = 3140 Hz f = 3380 Hz f = 3860 Hz f = 4600 Hz and above Transmit Gain Varia- GXAL Sinusoidal test method*, reference level = 0 dBm0: tion with Signal VFXI = -40 dBm0 to +3 dBm0 Level VFXI = -50 dBm0 to -40 dBm0 VFXI = -55 dBm0 to -50 dBm0 Receive Gain AbsoGRA Receive gain programmed to -6 dB, apply lute Accuracy 0 dBm0 signal to DR, measure VRCV, RL = 100 k differential: 20 C to 70 C 0 C to 85 C -40 C to +85 C Relative Gain, -- Digital input 0 dBm0 signal, VFROP to VFRON f = 300 Hz to 3400 Hz -- Digital input 0 dBm0 signal, Relative Phase, VFROP to VFRON f = 300 Hz to 3400 Hz Receive Gain Varia- GRAG Measure receive gain over the range from tion with Promaximum to minimum setting, calculated grammed Gain deviation from the programmed gain relative to GRA at 0 dB, VDD = 5 V Receive Gain Varia- GRAF Relative to 1004 Hz, digital input = tion with Fre0 dBm0 code, minimum gain < GR < maxiquency, 600 mum gain, 0 dB path gain: Resistive Terminaf = below 3000 Hz tion f = 3140 Hz f = 3380 Hz f = 3860 Hz f = 4600 Hz and above Receive Gain Varia- GRAL Sinusoidal test method*, tion with Signal reference level = 0 dBm0: Level IPCM digital level = -40 dBm0 to +3 dBm0 IPCM digital level = -50 dBm0 to -40 dBm0 IPCM digital level = -55 dBm0 to -50 dBm0 * Applied to all four channels. Min Typ Max Unit -- -- -- -- -- -0.125 -0.57 -0.735 -- -- -50 -40 -40 -55 -3.5 0.04 0.01 -0.03 -9.0 -- -30 -26 -30 -30 0 0.135 0.125 0.015 -8.98 -32 dB dB dB dB dB dB dB dB dB dB -0.25 -0.50 -1.40 -- -- -- 0.25 0.50 1.40 dB dB dB -- -0.25 -0.30 -0.01 -0.25 -0.1 0.15 -- -- -- -- -- -- 0.25 0.30 0.01 0.25 -0.1 dB dB dB dB Degrees dB -0.125 -0.57 -0.735 -- -- 0.04 0.04 -0.550 -10.7 -- 0.125 0.125 0.015 -8.98 -28 dB dB dB dB dB -0.25 -0.50 -1.40 -- -- -- 0.25 0.50 1.40 dB dB dB 30 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Electrical Characteristics (continued) Noise Characteristics Table 12. Per-Channel Noise Characteristics Parameter Transmit Noise, C-Message Weighted Transmit Noise, P-Message Weighted Receive Noise, C-Message Weighted Receive Noise, P-Message Weighted Noise, Single Frequency Power Supply Rejection, Transmit Symbol NXC NXP NRC NRP NRS PSRX Test Conditions 0 dB transmit gain* 0 dB transmit gain* 0 dB receive gain, digital pattern corresponding to idle PCM code, -law 0 dB receive gain, digital pattern corresponding to idle PCM code, A-law f = 0 kHz to 100 kHz, loop around measurement, VVFxI = 0 Vrms VDD = 5.0 VDC + 100 mVrms f = 0 kHz to 4 kHz f = 4 kHz to 50 kHz C-message weighted Measured on VFROP, VDD = 5.0 VDC + 100 mVrms: f = 0 kHz to 4 kHz f = 4 kHz to 25 kHz f = 25 kHz to 50 kHz 0 dBm0, 300 Hz to 3400 Hz signal applied to VVFxI, transmit gain set to 0 dB: 4600 Hz to 7600 Hz 7600 Hz to 8400 Hz 8.4 kHz to 50 kHz Min -- -- -- -- -- Typ -- -- -- -- -- Max 18 -68 13 -75 -53 Unit dBrnC0 dBm0p dBrnC0 dBm0p dBm0 36 30 -- -- -- -- dBC dBC Power Supply Rejection, Receive PSRR 36 40 36 -- -- -- -- -- -- dBC dBC dBC Spurious Out-of-Band Signals at the Channel Outputs SOS -- -- -- -- -- -- -30 -40 -30 dB dB dB * RTZ and CTZ paths open. All channels active. Agere Systems Inc. 31 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Electrical Characteristics (continued) Distortion and Group Delay Table 13. Distortion and Group Delay Parameter Symbol Signal to Total Distortion, Transmit or Receive, STDX STDR C-Message Weighted Single Frequency Distortion, SFDX Transmit Single Frequency Distortion, Receive Intermodulation Distortion SFDR Test Conditions Sinusoidal test method level: 3.0 dBm0 0 dBm0 0 dBm0 single frequency input, 200 Hz < fIN < 3400 Hz; measured at any other single frequency 0 dBm0 single frequency input, 200 Hz < fIN < 3400 Hz; measured at any other single frequency Transmit or receive, two frequencies in the range of 300 Hz to 3400 Hz f = 1600 Hz, 600 resistive termination f = 1600 Hz, 600 resistive termination Min 33 36 -- Typ -- -- -- Max -- -- -46 Unit dB dB dB -- -- -46 dB IMD -- -- -50 dB TX Group Delay, Absolute* RX Group Delay, Absolute* DXA DRX -- -- -- -- 370 220 s s * Absolute group delay is a function of time-slot assignment, and the maximum in this table refers to the (optimal minimum group delay) timeslot assignment. 32 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Electrical Characteristics (continued) Crosstalk Table 14. Crosstalk Parameter Transmit to Transmit Crosstalk, 0 dBm0 Level Transmit to Receive Crosstalk, 0 dBm0 Level Receive to Transmit Crosstalk, 0 dBm0 Level Receive to Receive Crosstalk, 0 dBm0 Level Symbol CTX-X CTX-R Test Conditions f = 300 Hz to 3400 Hz, any channel to any channel f = 300 Hz to 3400 Hz, any channel to any other channel In-channel f = 300 Hz to 3400 Hz, any channel to any other channel In-channel f = 300 Hz to 3400 Hz, any channel to any channel Min -- -- -- -- -- -- Typ -- -- -- -- -- -- Max -80 -80 -50 -80 -50 -80 Unit dB dB dB dB dB dB CTR-X CTR-R Agere Systems Inc. 33 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Timing Characteristics Table 15. Timing Characteristics Symbol fDCLK fBCLK Parameter Serial Bus Clock Frequency Allowable PCM Bus Clock Frequencies* (512 kHz minimum if linear encoding is selected.) Test Conditions -- -- Min -- -- -- -- -- -- -- -- -- 40 40 7 4 -- 4 7 7 4 tBCLK -- Typ -- 256 512 1024 2048 4096 8192 16384 -- 50 50 -- -- -- -- -- -- -- -- -- Max 4096 -- -- -- -- -- -- -- 100 ns in 100 ms = 1 ppm 60 60 -- -- 9 -- -- -- -- 125 s - tBCLK 9 Unit kHz kHz kHz kHz kHz kHz kHz kHz -- % % ns ns ns ns ns ns ns ns ns -- -- -- tCSSETUP tCSHOLD tSXDLY tSDHOLD tSDSETUP tFSSETUP tFSHOLD tFSWIDTH tXDLY Jitter of BCLK Serial Bus Clock Duty Cycle PCM Bus Clock Duty Cycle Chip Select Setup Time, Normal Mode Chip Select Hold Time, Normal Mode Serial Bus Output Data Delay, Normal Mode Serial Bus Input Data Hold Time, Normal Mode Serial Bus Input Data Setup Time, Normal Mode Frame Strobe Setup Time Frame Strobe Hold Time Frame Strobe Width PCM Bus Output Data Delay -- -- -- Serial clock frequency = 4.096 MHz Serial clock frequency = 4.096 MHz Serial clock frequency = 4.096 MHz Serial clock frequency = 4.096 MHz Serial clock frequency = 4.096 MHz PCM clock frequency = 16.384 MHz PCM clock frequency = 16.384 MHz FS synchronous with BCLK PCM clock frequency = 16.384 MHz * PCM clock (BCLK) must be synchronous with both FS and MCLK, if used. If MCLK is used, then the rising edge of MCLK must coincide with the rising edge of BCLK within 10 ns. The tSXBDLY delay is from either DCLK or CS, whichever transition is later, for the first bit of the byte. 34 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Timing Characteristics (continued) Table 15. Timing Characteristics (continued) Symbol tIDHOLD Parameter PCM Bus Input Data Hold Time Test Conditions Min 4 7 -- Typ -- -- -- Max -- -- 8 Unit ns ns ns PCM clock frequency = 16.384 MHz PCM clock frequency tIDSETUP PCM Bus Input Data Setup Time = 16.384 MHz Clock Edge Rise Time Serial clock frequency tRISE = 4.096 MHz, PCM clock frequency = 16.384 MHz Clock Edge Fall Time Serial clock frequency tFALL = 4.096 MHz, PCM clock frequency = 16.384 MHz Line Driver Rise/Fall Time (DO IL = 15 mA, tRISE, tFALL and DX outputs) CLOAD = 100 pF tCSBHOLD Chip Select Hold Time, Byte-by- Serial clock frequency Byte Mode = 4.096 MHz Serial Bus Output Data Delay, Serial clock frequency tSXBDLY Byte-by-Byte Mode = 4.096 MHz Serial clock frequency tCSBSETUP Chip Select Setup Time, Byteby-Byte Mode = 4.096 MHz Serial clock frequency tSDBHOLD Serial Bus Data Hold Time, Byte-by-Byte Mode = 4.096 MHz Serial clock frequency tSDBSETUP Serial Bus Data Setup Time, Byte-by-Byte Mode = 4.096 MHz tCSBHOLD Chip Select Hold Time, Byte-by- Serial clock frequency Byte Mode = 4.096 MHz -- -- 8 ns -- 4 -- 7 4 7 4 -- -- -- -- -- -- -- 30 -- 9 -- -- -- -- ns ns ns ns ns ns ns * PCM clock (BCLK) must be synchronous with both FS and MCLK, if used. If MCLK is used, then the rising edge of MCLK must coincide with the rising edge of BCLK within 10 ns. The tSXBDLY delay is from either DCLK or CS, whichever transition is later, for the first bit of the byte. Table 16. Echo Canceller Characteristics Parameter Echo Return Loss Convergence Time Symbol -- -- Test Conditions -- -- Min -- -- Typ 45 100+ Max -- -- Unit dB dB/s Agere Systems Inc. 35 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Bus Timing Diagrams Normal Mode tCSHOLD CS tCSSETUP DCLK 1 2 3 4 5 6 7 8 9 LSB DO tSXDLY 0 1 2 tSDHOLD 0 1 tSDSETUP 5-7185.MOD(F) 3 4 5 6 7 DI 2 3 4 5 6 7 Figure 21. Serial Interface Timing, Normal Mode (One Byte Transfer Shown) Byte-by-Byte Mode CS tCSBHOLD tCSBSETUP DCLK 0 1 tSDBSETUP DO 0 1 2 tSDBHOLD LSB DI 0 1 tSDBSETUP 5-7186e (F) 2 3 tSXBDLY 3 4 5 6 7 4 5 6 7 MSB 2 3 4 5 6 7 Figure 22. Serial Interface Timing, Byte-by-Byte Mode (One Byte Transfer and Gapped DCLK Shown) 36 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Bus Timing Diagrams (continued) PCM Interface Only the first time slot is shown, and the bit offset is assumed to be zero. Notice that the PCM bus transfers the most significant bit of the time slot first, consistent with normal telephony practice. The diagram shows a bit offset of zero from frame strobe, and for nonzero values of RXBITOFF and TXBITOFF, the relationship between FS and DX or DR will be shifted by the programmed number of cycles of BCLK. BCLK can be any value from 256 kHz (four time slots) to 16.384 MHz (256 time slots). The frame strobe signal is at a rate of 8 kHz and must be synchronous with the PCM bus clock (BCLK). Sixteen-bit linear code uses two consecutive time slots with LSB transmitted/ received first. See the Clocking Considerations section for the relationship between BCLK and MCLK, if used. ADDITIONAL TIME SLOTS TIME SLOT 0 tFSWIDTH FS tFSSETUP tFSHOLD BCLK 1 2 3 4 5 6 7 8 9 DX tXDLY 1 2 3 tIDHOLD 4 5 6 7 8 SIGN BIT DR 1 2 LSB 4 5 6 7 8 3 tIDSETUP 5-7188.e(F) Figure 23. PCM Bus Timing (Diagram Shown has Bit Offset of Zero and Minimum Width of FS) Agere Systems Inc. 37 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Software Interface Table 17. Memory Mapping With the exceptions noted, all of these memory locations may be read to determine the state of the controls contained therein. In the following table, bit 0 is the LSB (transmitted first on the serial interface) and bit 7 is the most significant bit of the byte. Unused bits in an address or multibyte address should be loaded as zero. All of the memory locations can be programmed on a per-channel basis. Note that the entire coefficient set for a channel (or all four channels) may be loaded with one command. Address (decimal) 0--127 128 Number of Bits Used 1024 4 Default Value See Table 18 0x00 Control Name HBALTAPS* RESCTRL Name/Description Balance impedance tap coefficients. Reset address. Writing a 1 in the used positions causes a reset as defined by the bit definition. This reset remains in force until the bit is written as a 0. Standby/active control. Bit offset for receive direction. Time-slot offset for receive direction. CHACTIVE RXBITOFF RXOFF GRX1* GRX2* NORMCTRL* NESCTRL* LMSGAIN* TDETCTRL* CTZCTRL* LMSCTRL* RECCTRL* SDCTRL* SDTSI GTX2* ZEQCTRL* GTX1* TXBITOFF TXOFF PCMCTRL SLICTS 129 130 131 132--133 134--135 136 137 138 139 140--143 144 145 146 147 148--149 150--152 153--154 155 156 157 158 1 3 8 11 11 6 3 8 6 31 3 5 7 7 12 21 12 3 8 7 6 Control of gain affecting receive direction gain transfer. Control of gain sensitive to impedance and SLIC parameter choices, receive direction. 0x25 Peak and far-end speech detector control. 0x06 Near-end speech detector control. 0xee Adaptation control address. 0x00 Data call control address. 0x07ed0000 CTZ bleed coefficients. 0x01 Adaptation leak values. 0x00 Residual echo control. 0x19 RTZ, transmit analog gain (XAG), and analog loopback controls. (17* Internal time-slot interchanger. Default sets external pins to channel #) state referenced in this data sheet. 0x0400 Control of gain affecting transmit direction gain transfer. 0x000000 Coefficients for the equalization stage that accommodates current-sensing SLICs. 0x051a Control of gain sensitive to impedance and SLIC parameter choices, transmit direction. 0x00 Bit offset for transmit direction. (16* Time-slot offset for transmit direction. channel #) 0x00 PCM control address. 0x0c SLIC 3-state control address. A 1 enables the corresponding SLIC pin to operate as an output pin. 0x00 0x00 (16* channel #) 0x0400 0x01ac * The coefficients to be entered can be obtained from the Aquarium coefficient software. 38 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Software Interface (continued) Table 17. Memory Mapping (continued) Control Name SLICWR SLICRD Address (decimal) 159 160 Number of Bits Used 6 6 Default Value 0x00 -- Name/Description Data to be written to the SLIC latches if the corresponding bit is set in the SLICTS control word. Current actual state of the SLIC pins. This will be the same as SLICWR for those pins configured as outputs. All other positions will reflect the actual state of the external pin. A write operation to this word will be ignored, and within one PCM frame (125 s), the data will be overwritten. Test address for serial interface verification. Read-only indicator of a data call in progress. Do not write this register. Factory test only, do not access. VERIFY DATACALL -- 162 167 254--255 8 1 16 -- -- -- Table 18. Control Bit Definition The following table shows the control bit assignments in the memory control addresses. In all control bit cases, the bit being set places the function into the active mode as defined in the function column. Control Name Bit (Address, Decimal) Function Assignment(s) [Address, Hex] HBALTAPS 0--1023 Balance impedance coefficients. Default value is 0x00 for all bytes except (0--127) for addresses 3 and 5, which are 0x80, and address 69, which is 0x88. [0x00--0x7f] RESCTRL 4--7 Not used, load as 0s. (128) 3 A one resets the state associated with special data call processing. [0x80] 2 A one resets the echo canceller coefficients to 0 when channel is active. 1 A one resets all other internal states. Does not affect programmed registers. 0 Reset all control addresses to default values. Note that setting this bit will result in it and all others of this word becoming cleared on the next PCM frame as a normal part of this control reset functionality. Also, the state reset bits (1--3) are cleared before they are acted upon if this bit is raised; hence, it is not possible to reset both state and control by writing 0x0F to RESCTRL. If such an action is desired, it is necessary to first reset control by writing 0x01 and then, in a subsequent frame, write first 0x0E and then 0x00. Alternatively, hardware reset can be used to reset all control and state. It is necessary to wait at least 256 s after asserting this bit before initiating any other serial I/O transactions. Load as 0s. Active/Standby mode. A 0 causes the channel to enter standby (low power) mode and disables the PCM interface for this channel. A 1 activates the channel and the corresponding PCM bus interface. Default is 0. CHACTIVE (129) [0x81] 1--7 0 Agere Systems Inc. 39 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Software Interface (continued) Table 18. Control Bit Definitions (continued) Function Control Name Bit (Address, Decimal) Assignments [Address, Hex] RXBITOFF 5--7 Receive direction bit offset for the FS signal. Defaults to 0. These 3 bits (130) can be thought of as the least significant bits (RXOFF contains the more [0x82] significant bits) of a bit counter that determines the location of the first bit of the PCM data from FS. 0--4 Load as 0. RXOFF 0--7 Receive time-slot assignment. Defaults to (16 * channel number). Each (131) time slot represents 8 bits, allow for two time slots when using linear [0x83] mode. GRX1 0--10 Gain adjustment for gain transfer stage in receive direction. Defaults to (132--133) 0x0400 (0 dB). This is an 11-bit multiply operation with a maximum gain of 2 (6 dB). 0 dB is the maximum recommended setting. [0x84--0x85] 0--10 Gain adjustment for tweak gain stage in receive direction. Defaults to GRX2 (134--135) 0x01ac (-7.58 dB). This is an 11-bit multiply operation with a maximum gain of 2 (6 dB). 0 dB is the maximum recommended setting. [0x86--0x87] NORMCTRL 6--7 Load as 0s. (136) 3--5 Peak detector tweaking control. Use default Bit Number Function [0x88] of 4. (dB) 5 4 3 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Bit Number 2 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0.0 -3.01 -6.02 -9.03 -12.04 -15.05 -18.06 -21.07 Function (dBm0) -57 -54 -51 -48 -45 -42 -39 -36 0--2 Far-end speech detector threshold. Use default of 5. 40 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Software Interface (continued) Table 18. Control Bit Definitions (continued) Control Name (Address, Decimal) [Address, Hex] NESCTRL (137) [0x89] Bit Assignments 3--7 2 0--1 Function LMSGAIN (138) [0x8a] 6--7 3--5 0--2 TDETCTRL (139) [0x8b] 6--7 5 4 3 2 1 0 Load as 0s. Enable near-end speech detector. Defaults to 1 (active). Threshold for the near-end speech detecBit Function (dB) tor. Default is 2 (-6 dB). Number (Threshold =) 1 0 0 0 0.0 0 1 -3.5 1 0 -6.0 1 1 -9.5 Length of echo canceller (8, 16, 32, 64 Bit Function taps). Defaults to 3 (64 taps). Number 7 6 0 0 8 taps 0 1 16 taps 1 0 32 taps 1 1 64 taps Relative adaptive gain of the two IIR taps in the echo canceller. Defaults to 5. A setting of 0 provides no adaptive loop gain. Loop gain for adaptation algorithm. Bit Number Function Default is 6. (Gain =) 2 1 0 0 0 0 0.0078 0 0 1 0.0156 0 1 0 0.0313 0 1 1 0.0625 1 0 0 0.1250 1 0 1 0.2500 1 1 0 0.5000 1 1 1 1.000 Load as 0. This bit being set allows the echo canceller coefficients developed offline during a data call to be captured and saved for potential use during the next data call. Default is 0 (do not capture). This bit enables the echo canceller to continue to adapt during a data call. Default is 0 (do not adapt during a data call). This bit, when set, enables the use of the internal logic to determine the proper time for the off-line adaptation during a data call. Default is 0. Selects the internal set of hybrid balance network coefficients to use on a data call. Default is 0. This bit, when set to a 1, clears the H register at the start of a data call. Default is 0. This bit being set freezes the echo canceller. Default is 0. Agere Systems Inc. 41 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Software Interface (continued) Table 18. Control Bit Definitions (continued) Control Name (Address, Decimal) [Address, Hex] CTZCTRL (140--143) [0x8c--0x8f] LMSCTRL (144) [0x90] RECCTRL (145) [0x91] Bit Assignments 0--30 Function Coefficients for the CTZ termination bleed. Defaults to 0x07ed0000. 3--7 0--2 5--7 4 3 0--2 Load as 0s. Leak coefficient for LMS adaptation algorithm. Defaults to 1. Load as 0s. Noise match enable (comfort noise). Defaults to 0 (disabled). Enable residual echo control. Defaults to 0 (disabled). Residual echo control sensitivity factor. Bit Number Function Defaults to 0. (dB) 21 0 (Threshold =) 00 0 0.0 00 1 -3.5 01 0 -6.0 01 1 -9.5 10 0 -12.0 10 1 -15.5 11 0 -18.0 11 1 -21.6 Load as 0. Enable analog loopback. Defaults to 0 (no loopback). RTZ gain. Defaults to 3 (equal level point value of 3 * 0.075 = 0.225). Transmit analog gain (XAG). Defaults to 1 Bit Number Function (6 dB) gain. (dB) 21 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0.0 6.02 12.04 18.06 24.08 SDCTRL (146) [0x92] 7 6 3--5 0--2 SDTSI (147) [0x93] 7 6 4--5 3 2 0--1 GTX2 (148--149) [0x94--0x95] 0--11 Load as 0. Digital loopback, loopback from receive to transmit at the sigma-delta converters (digital loopback 2). Defaults to 0 (no loopback). Digital channel feeding this analog receive channel. Defaults to channel number. Send idle channel code (alternating bits) to this analog receive path. Defaults to 0 (do not send idle channel code). Loopback from transmit to receive at the sigma-delta converters (digital loopback 3). Defaults to 0 (no loopback). Analog channel feeding this digital channel in the transmit direction. Defaults to channel number. Gain control for gain transfer stage in transmit direction. Defaults to 0x0400 (0 dB). This is a 12-bit multiply operation with a maximum gain of 4 (12 dB). 42 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Software Interface (continued) Table 18. Control Bit Definitions (continued) Control Name (Address, Decimal) [Address, Hex] ZEQCTRL (150--152) [0x96--0x98] GTX1 (153--154) [0x99--0x9a] TXBITOFF (155) [0x9b] Bit Assignments 0--20 Function Coefficients for the equalization stage that accommodates current-sensing SLICs. Defaults to 0x000000. Gain control for tweak gain stage in transmit direction. Defaults to 0x051a (2.11 dB). This is a 12-bit multiply operation with a maximum gain of 4 (12 dB). Transmit direction bit offset for the FS signal. Defaults to 0. These 3 bits can be thought of as the least significant bits (TXOFF contains the more significant bits) of a bit counter that determines the location of the first bit of the PCM data from FS. Load as 0. Transmit time-slot assignment. Defaults to (16 * channel number). Each time slot represents 8 bits, allow for two time slots when using linear mode. 3-state transmit PCM interface. Defaults to 0. A 1 forces the PCM interface into a high-impedance state during its assigned time slot on the PCM bus. Placing the channel in standby mode also forces a high-impedance condition on the transmit interface. Transmit zeroes instead of data. Defaults to 0 (off). Load as 0. Place idle channel code on receive path. Defaults to 0 (off). Loopback receive to transmit at PCM conversion interface (digital loopback 1). Defaults to 0 (no loopback). Loopback transmit to receive at PCM conversion interface (digital loopback 4). Defaults to 0 (no loopback). Linear/companded. A 1 sets 16-bit linear mode with two adjacent time slots used, LSB transmitted first. Linear data is in two's complement form. A 0 sets companded mode with only one time slot used, and MSB transmitted first. Defaults to 0. -law or A-law. A 0 sets -law mode, and a 1 sets A-law mode. This bit has no effect if bit 1 of this address is set to 1. Defaults to 0 (-law). Load as 0. Controls the drivers for the corresponding SLIC latches. A 1 enables the pin as an output. Defaults to 0x0c (bits 2 and 3 set, the rest cleared). Load as 0. SLIC data latches. If the corresponding bit in the SLICTS address is set for an output, the device will drive the corresponding bit according to the contents of this address. Writes are performed within 125 s. Wait 125 s before a subsequent write to the same channel or between write all channel commands. Default is 0. Not used, ignore on a codec read command addressing this location. Reports the actual state of the SLIC pins. Anything written to this address is ignored. Updates within 125 s. Test location for serial interface. This location has no internal use, but merely latches write data for the purpose of testing the serial interface. This register does not clear with reset. This bit is set to a 1 if a data call is in progress. Do not attempt to write this register. Internal state control bits; do not write and ignore on read. 0--11 5--7 TXOFF (156) [0x9c] PCMCTRL (157) [0x9d] 0--4 0--7 7 6 5 4 3 2 1 0 SLICTS (158) [0x9e] SLICWR (159) [0x9f] 6--7 0--5 6--7 0--5 SLICRD (160) [0xa0] VERIFY (162) [0xa2] DATACALL (167) [0xa7] 6--7 0--5 0--7 5 0--4, 6, 7 Agere Systems Inc. 43 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Applications The following reference circuit shows a complete schematic for interfacing to the Agere L9215G SLIC. All ac parameters are programmed by the T8534. Note that this implementation differentiates itself in that no external components are required in the ac interface to provide a dc termination impedance or for stability. For illustration purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used. Also, this example illustrates the device using programmable overhead and current limit. VBAT1 CBAT1 DBAT1 CRT 0.1 F RRT 383 k FUSIBLE OR PTC 50 VBAT1 50 AGERE L7591 PT 0.1 F VBAT2 VCC CBAT2 0.1 F CCC 0.1 F AGND ICM TRGDET ground key not used VBAT1 RTFLT BGND VBAT2 VCC ITR RGX 4750 VTX CTX 0.1 F TXI CC1 0.1 F VITR VFXI RVFxI* 20 M DX0 DR0 VFROP VFRON T8534 DX1 DR1 PCM HIGHWAY DCOUT PR L9215G FUSIBLE OR PTC RCVP FROM PROGRAMMABLE D/A VOLTAGE SOURCE OVH RCVN VPROG rate of battery reversal not ramped FS B2 B1 B0 RINGIN RPD1 10 k PPMIN CPPM 10 nF B2 B1 SLIC4a SLIC3a SLIC2a SLIC1a SLIC0a DGND VDD BCLK VREF CF1 CF1 0.22 F CF2 FB1 FB2 NSTAT BR SYNC AND CLOCK CF2 0.1 F CRING 0.47 F B0 BR FROM/TO CONTROL NSTAT PPM 0.5 Vrms VDD 12-3534.z (F) *RVFxI is required for complex terminations. Optional for resistive terminations. Figure 24. POTS Interface 44 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Outline Diagrams 68-Pin PLCC Dimensions are in millimeters. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed footprint drawings to assist your design efforts, please contact your Agere Sales Representative. 25.146 0.127 24.231 0.102 PIN #1 IDENTIFIER ZONE 9 1 61 10 60 24.231 0.102 25.146 0.127 26 44 27 43 5.080 MAX SEATING PLANE 0.10 1.27 TYP 0.330/0.533 0.51 MIN, TYP 5-2139(F) Agere Systems Inc. 45 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Outline Diagrams (continued) 64-Pin TQFP Dimensions are in millimeters. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed footprint drawings to assist your design efforts, please contact your Agere Sales Representative. 12.00 0.20 10.00 0.20 PIN #1 IDENTIFIER ZONE 64 49 1 48 10.00 0.20 12.00 0.20 16 33 17 32 DETAIL A DETAIL B 1.40 0.05 1.60 MAX SEATING PLANE 0.08 0.50 TYP 0.05/0.15 1.00 REF 0.25 GAGE PLANE SEATING PLANE 0.45/0.75 0.19/0.27 0.106/0.200 0.08 DETAIL B M DETAIL A 5-3080(F) 46 Agere Systems Inc. Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Outline Diagrams (continued) 44-Pin PLCC Dimensions are in millimeters. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed footprint drawings to assist your design efforts, please contact your Agere Sales Representative. 17.65 MAX 16.66 MAX PIN #1 IDENTIFIER ZONE 6 1 40 7 39 16.66 MAX 17.65 MAX 17 29 18 28 4.57 MAX SEATING PLANE 0.10 1.27 TYP 0.53 MAX 0.51 MIN TYP 5-2506(F) Agere Systems Inc. 47 T8533/34 Quad Programmable Line Card Signal Processor Preliminary Data Sheet July 2001 Ordering Information Device Code T-8533 - - - ML - D T-8534 - - - TL - DB T-8534 - - - ML - D Package 44-Pin PLCC, Dry-bagged 64-Pin TQFP, Dry pack tray 68-Pin PLCC, Dry-bagged Comcode 108269408 108420217 108269424 For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright (c) 2001 Agere Systems Inc. All Rights Reserved July 2001 DS01-250ALC (Replaces DS01-058ALC) |
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